VSI ECL-signal definition (draft Proposal)
IVS-TDC group (JN), CRL, Kashima
Purpose of this document:
Idea of variable speed signal assignment to the VSI (VLBI Standard Interface) connector and cables.
Define the combination between the occupied parallel data line and VSI data transfer rate, which is vary 64,128,256,1024 or 2048Mbps due to connected instrument. Also, general electrical signal characteristics should be defined with cable and circuit consideration.
VSI data rate and parallel data transfer is proposed in Table1. This total data rate and active data line combinations are based on currently existing VLBI instrument . As for 1024Mbps mode, two clock frequency mode are prepared. Because the 64MHz clock data transfer is under experiment.
Table 1. VSI data rate and connector, parallel line expansion
|Input / output|
|Connector-1 ||Connector-2 ||Connector-3,4
|64M ||8 ||DATA0-DATA7 ||Not used |
|128M ||16 ||DATA0-DATA7 ||Not used |
|256M ||32 ||DATA0-DATA7 ||Not used |
|1024M ||32 ||DATA0-DATA15 ||DATA16-DATA31 |
|1024M ||64 ||DATA0-DATA15 ||Not used |
|2048M ||64 ||DATA0-DATA15 ||DATA16-DATA31 |
|(4096M) ||64 ||DATA0-DATA15 ||DATA16-DATA31 ||DATA32-47, 48-63
The VSI electrical characteristics is based on differential- ECL connection. This is the most reliable between separated unit. The "ECL10K" is recommended. The "ECL10KH" is also recommended in high speed 64MHz operation@for better tr and tf. The time-digital characteristics required at input of a DIB or a correlator is in Table 2.
Fig.1 VSI input signal characteristc definition.
Table 2. Electrical time characteristics definition
|8 ||125 ||62.5 ||62.5+/-3ns ||5 ||5
|16 ||62.5 ||31.25 ||31.25+/-3ns ||5 ||5
|32 ||31.25 ||15.625 ||15.625+/-3ns ||5 ||5
|64 ||15.625 ||7.8125 ||7.8125+/-3ns ||3 ||3
The electrical definition in table2 should be confirmed at the VSI cable in front of a DIB or a correlator input. The VSI maximum 20 meter cable and a terminated resistor Rt is needed in measurement as in figure 2. For the successful international multi vendor connection, detailed measurement procedure should be prepared. If a poor quality DAB or DOB emerged, the cable length will be shorten to cure the case.
Fig.2 VSI input signal characteristc measurement.
Standard electrical circuit recommendations:
The VSI -TDC should show an example of ECL driver and differential receiver which qualify the characteristics in table 2. This will useful for the future design and new VLBI developing countries. The Figure 3 shows an example of driver / receiver combination. The resistors Ra and Rt will be determined after the VSI connector / cable assembly selection. It can be adjusted to the twisted pair line impedance around 100 ohm. The optimal selection minimize the reflection and enable long distance transmission. Several capacitor and diodes not shown in fig.3 also increase its performance.
Fig.3 VSI recommendation for differential driver/receiver.
Although, the 64MHz clock is the key to over 2048Mbps, the VSI input parameters becomes very critical in this frequency. Especially, slight squeue occurred between the data and clock will bring vast increase of bit-error rate and faulty data synchronize. Electrical measurement and standard circuit will be able to determined after the lab experiment with determined VSI connector and VSI cables.
Current Japanese 1024Mbps VLBI is completed on stable 32MHz by 32 paralleled line. We see less problem in this clock frequency.
March 31, 1999