Direct Microrolling Processing on a Silicon Wafer

K Aoki, K Ishiguro, M Denokami, Y Tanahashi… - small, 2017 - Wiley Online Library
K Aoki, K Ishiguro, M Denokami, Y Tanahashi, K Furusawa, N Sekine, T Adschiri, M Fujii
small, 2017Wiley Online Library
Although, varieties of micro‐to nanoscale fabrication technologies have been invented and
refined for silicon (Si) processing because Si is the basic material of integrated circuits, the
layouts are based on layer‐by‐layer approaches, making it difficult to realize three‐
dimensional (3D) structures with complicated shapes normal to the planar surface (along the
out‐of‐plane direction) of the wafers used. Here, a novel and direct Si‐processing
technology that enables to bend thin layers of Si surfaces into various 3D curved structures …
Although, varieties of micro‐ to nanoscale fabrication technologies have been invented and refined for silicon (Si) processing because Si is the basic material of integrated circuits, the layouts are based on layer‐by‐layer approaches, making it difficult to realize three‐dimensional (3D) structures with complicated shapes normal to the planar surface (along the out‐of‐plane direction) of the wafers used. Here, a novel and direct Si‐processing technology that enables to bend thin layers of Si surfaces into various 3D curved structures at the micrometer scale is introduced. This bending is achieved by porosifying a Si wafer surface using anodic oxidation and then performing conventional photolithography patterning and wet etching. The porosity gradient in the depth direction gives rise to a stress‐internalized layer in which self‐rolling action is induced via subsequent patterning and wet etching. A subsequent oxidation process further enhances the curvature deformation, leading to the formation of tubes, for example. The rolling directions can be controlled by 2D patterning of the porous Si layer, which is explained well from a structural dynamics perspective. This technology has a wide range of capabilities for realizing 3D structures on Si substrates, enabling new design possibilities for Si‐based on‐chip devices.
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