A layout-oriented routing method for low-latency hpc networks

R Kawano, H Nakahara, I Fujiwara… - … on Information and …, 2017 - search.ieice.org
IEICE TRANSACTIONS on Information and Systems, 2017search.ieice.org
End-to-end network latency has become an important issue for parallel application on large-
scale high performance computing (HPC) systems. It has been reported that randomly-
connected inter-switch networks can lower the end-to-end network latency. This latency
reduction is established in exchange for a large amount of routing information. That is,
minimal routing on irregular networks is achieved by using routing tables for all destinations
in the networks. In this work, a novel distributed routing method called LOREN (Layout …
End-to-end network latency has become an important issue for parallel application on large-scale high performance computing (HPC) systems. It has been reported that randomly-connected inter-switch networks can lower the end-to-end network latency. This latency reduction is established in exchange for a large amount of routing information. That is, minimal routing on irregular networks is achieved by using routing tables for all destinations in the networks. In this work, a novel distributed routing method called LOREN (Layout-Oriented Routing with Entries for Neighbors) to achieve low-latency with a small routing table is proposed for irregular networks whose link length is limited. The routing tables contain both physically and topologically nearby neighbor nodes to ensure livelock-freedom and a small number of hops between nodes. Experimental results show that LOREN reduces the average latencies by 5.8% and improves the network throughput by up to 62% compared with a conventional compact routing method. Moreover, the number of required routing table entries is reduced by up to 91%, which improves scalability and flexibility for implementation.
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