The 95th KARC Colloquium
The 95th KARC Colloquium was ended. Thank you for the participation.
| Date&Time | Tuesday, August 26th, 2008 14：00-16：00 |
| Place | Conference Room, 3F, Laboratory Bldg 2,Kobe Advanced ICT Research Center |
| Lecturer1 | “ On Effective Computation with Single Electron Tunneling Devices” |
| Speaker | Dr. Sorin Cotofana Associate Professor Fac. of Elec. Eng., Computer Science, and Mathematics,Delft University of Technology, The Netherlands |
| Abstract | It is generally accepted that fundamental physical limitations will eventually inhibit further (C)MOS feature size reduction. Several emerging nano-electronic technologies with greater scaling potential, such as Single Electron Tunnelling (SET), are currently under investigation. Each of those exhibits its own switching behavior, resulting in new paradigms for logic design and computation. In this talk we present an analysis of various design styles that might be potentially utilized in conjunction with SET devices. First, we discuss and compare the following three synchronous SET designs styles: CMOS-alike logic, based on SET transistors; Single Electron Encoded Logic, based on threshold gates that utilize the intrinsic behavior of SET tunnel junctions; and Electron Counting logic, based on direct encoding of integers as charge combined with computation via charge transport. Subsequently, we discuss SET based delay insensitive computations and fluctuation based computation. Our analysis indicates that the more promising approaches are the ones that rely on the specific properties and behavior of the SET devices. |
| Lecturer2 | ”Novel Single-Electron Function Device Based on a Nanodot Array with Multiple Inputs and Multiple Outputs” |
| Speaker | Dr. Yasuo Takahashi Professor Graduate School of Information Science and Technology Hokkaido University |
| Abstract | The small feature sizes of CMOSLSI have made it increasingly difficult to realize both high functionality and low power consumption at the same time. For the operation of Single Electron devices, on the other hand, a small feature size is a merit rather than an obstacle and it is expected that such devices will be able to operate with extreme low power consumption. Single Electron devices have some drawbacks, however, a major problem being caused by the variability of their sizes. We propose to use devices composed of arrays of a large number of nanodots towards this problem’s solution, which potentially offers the benefit of retaining the ability for low power as well as high functionality. A feature of this Single Electron device is that it can be configured as a gate with many inputs as well as many outputs attached. Aiming for high functionality and many degrees of freedom, we experimentally realized the device on an Si wafer, and evaluated its basic characteristics. |
| Language | English |
| Admission | Free |
| Organizer | Ferdinand Peper Senior Researcher, Nano ICT Group, Advanced ICT Research Center National Institute of Information and Communications Technology |