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Fault-tolerance in nanocomputers
Abstract
In the nanotechnology group we develop the theory behind the design of computers based on nanometer-sized devices. As devices are unreliable at nanometer-scale integration densities, error correction methods are required to achieve highly reliable computation. We will construct the concepts underlying fault-tolerant nanocomputers by combining the theory of error-correcting codes with cellular automaton-based nanocomputers, which is a model that faciltates efficient mass-production. To realize this idea, the contractor investigates error correcting codes that can be suitably combined with cellular automata. The obtained results will then be applied in the framework of cellular automaton-based nanocomputers.
Contractor
Himeji Institute of Technology, Faculty of Engineering, Dept. Computer Engineering.